Functional Verification is defined as the process of verifying that an RTL (Synthesizable Verilog, VHDL, SystemVerilog) design meets its specification from a functional perspective.  

RTL Verification is usually divided into two discreet areas. Functional verification, and physical verification. Functional verification establishes that the design under test (DUT) implements the functionality of the specification correctly. Physical verification checks that the synthesis, implementation and back-end flow maintain the same functionality in their level of abstraction.

Functional verification is usually one of the most challenging areas in chip design. Functional verification aims to verify that a specific model implements the specification correctly. To implement the specification the design team interprets sentences and paragraphs describing functionality into RTL code. Since both the process is manual and the specification inevitably leaves room for interpretation, there are numerous areas for RTL designers to make mistakes.

Due to the infinite number of potential design states in large designs, functional verification usually is unable to exhaustively check a design. Two main methods are used to verify within the complexity constraints. The first is simulation, the second if formal property checking.     

Physical verification may include gate-level simulation, Static timing analysis, and formal equivalence checking. These are tools aimed at verifying that the synthesis tool created a valid and equivalent net-list to the original RTL. With a comprehensive list of design rules, if these tools are employed correctly and each error reported by the tools is adequately verified this process should yield a 1 to 1 equivalence of the design to the resulting product in silicon.  

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