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LEADERSHIP SEMINAR - Presentations

All presentations posted here are posted with the permission of the topic presenter

Note: The assignment given to presenters was to present a few slides as a basis for questions to be discussed during a group session of verification leaders. The slides do not reflect the ensuing discussion and conclusions.  

Summer Session 2008

Verification reuse & VIP (Alvarion & Samsung)

Formal Verification (Mellanox & Gila Logic)

Environment Completeness (Cadence & Broadcom)

Random-> Direct (Saifun)

Hardware Software integration (Nokia Siemens & Mellanox)

Coverage Completeness + Code (Marvell & Ace Verification)

Fall Session 2007

Simulation Performance  (PMC & Windbond)

Verification Team (Microsem & Saifun)

Test Automation (CEVA-DSP &  PMC Sierra)

Improving Debug (Saifun & TI)

Verification Reuse (TI & Broadlight)

Assertion Based Verification (Ace Verification & Saifun)

Environment Completeness (Ace Verification & TI)

 

Summer Session 2006

Verification Team (Saifun & Transchip)

Verification Reuse (Cisco & Cadence)

Predictability (Starcore & Broadlight)

Formal Verification (Cisco & Saifun)

Coverage Completeness (Wintegra & Marvell)

Environment Completeness (Ace Verification)

Architecture of Environment (TI & Siverge)

Building a Testplan (Discretix & Marvell)

 

Winter Session 2005-2006 Group 1:

Regression Methodology By: Einat (Intel)

Intro to System Verilog - By: Efrat (Cadence)

System Verilog Assertions - By: Dafna (Alvarion)

Pre-Silicon to Post-Silicon -  By: Hillel (Freescale)

Hardware Accelerators By: Rotem (Alvarion)

Reuse Methodology By: Arie (Passave)  

Coverage Completion By: Hadar (Zoran)

Winter Session 2005-2006 Group 2:  

Predictability in Verification - By: Misha (Corrigent)

Verification Reuse Methodology - By: Itai (Texas Instruments)

Verification Environment Architecture - By: Sergey (Sandisk)

Pre-Silicon to Post-Silicon - By: Ran (Ceva-DSP)

Design for Verification - By: Amit (Freescale Semiconductor)

Classic Mistakes By: Racheli (Flexlight Networks)

Verification Team By: Talya (Intel)

Coverage Completeness By: Ofer (RAD)

 

 

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